Instruction Set Architecture
Each thread has access to 12 general purpose registers, and a standard 3-operand instruction set is used for programming the thread. The instruction set is encoded densely, encoding most instructions in 16 bits, where 11 bits are used for specifying 3 operands, and 5 bits are used to encode the opcode. Less frequently used instructions are encoded in 32 bits. The instruction set is a load-store instruction set. All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions.This acts like a very small instruction cache, but its behavior can be predicted at compile time, making timing behavior as predictable as functional behavior. The instruction set natively supports events which enables the processor to stop a thread and restart it when an event is ready. In addition, a thread may be interrupted to deal with some external events.
Read more about this topic: XCore XS1-G4
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