Motorola 68000 - Instruction Set Details

Instruction Set Details

The standard addressing modes are:

• Register direct
  • data register, e.g. "D0"
  • address register, e.g. "A6"

• Register indirect
  • Simple address, e.g. (A0)
  • Address with post-increment, e.g. (A0)+
  • Address with pre-decrement, e.g. -(A0)
  • Address with a 16-bit signed offset, e.g. 16(A0)
  • Indexed register indirect with 8-bit signed offset e.g. 8(A0, D0) or 8(A0, A1)

Note that with (A0)+ and -(A0), the actual increment or decrement value is dependent on the operand size: a byte access increments the address register by 1, a word by 2, and a long by 4.

• PC (program counter) relative with displacement
  • Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful for position-independent code.
  • Relative with 8-bit signed offset with index, e.g. 8(PC, D2)

• Absolute memory location
  • Either a number, e.g. "$4000", or a symbolic name translated by the assembler
  • Most 68000 assemblers used the "$" symbol for hexadecimal, instead of "0x" or a trailing H.
  • There were 16 and 32-bit version of this addressing mode

• Immediate mode
  • Data stored in the instruction, e.g. "#400"

• Quick Immediate mode
  • 3 bit unsigned (or 8 bit signed with moveq) with value stored in Opcode
  • In addq and subq, 0 is the equivalent to 8
  • e.g. moveq #0,d0 was quicker than clr.l d0 (though both made d0 equal 0)

Plus: access to the status register, and, in later models, other special registers.

Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes (".b"), 16-bit words (".w"), and 32-bit longs (".l").

Most instructions are dyadic, that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were:

• Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU, DIVS, NEG (additive negation), and CMP (a sort of comparison done by subtracting the arguments and setting the status bits, but did not store the result)

• Binary Coded Decimal Arithmetic: ABCD, and SBCD

• Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)

• Shifting: (logical, i.e. right shifts put zero in the most significant bit) LSL, LSR, (arithmetic shifts, i.e. sign-extend the most significant bit) ASR, ASL, (Rotates through eXtend and not:) ROXL, ROXR, ROL, ROR

• Bit test and manipulation in memory: BSET (to 1), BCLR (to 0), BCHG (invert Bit) and BTST (set the Zero bit if tested bit is 0)

• Multiprocessing control: TAS, test-and-set, performed an indivisible bus operation, permitting semaphores to be used to synchronize several processors sharing a single memory

• Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from subroutine), RTE (return from exception, i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)

• Branch: Bcc (a branch where the "cc" specified one of 16 tests of the condition codes in the status register: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register).

• Decrement-and-branch: DBcc (where "cc" was as for the branch instructions) which decremented a D-register and branched to a destination provided the condition was still true and the register had not been decremented to -1. This use of -1 instead of 0 as the terminating value allowed the easy coding of loops which had to do nothing if the count was 0 to begin with, without the need for an additional check before entering the loop. This also facilitated nesting of DBcc.