Physical Implementation
The 8080 integrated circuit used non-saturated enhancement load nMOS gates, demanding extra voltages (for the load-gate bias). It was manufactured in a silicon gate process using a minimum feature size of 6 µm. A single layer of metal was used to interconnect the approximately 6,000 transistors in the design, but the higher resistance polysilicon layer, which required higher voltage for some interconnects, was implemented with transistor gates. The die size was approximately 20 mm².
Read more about this topic: Intel 8080
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“But alas! I never could keep a promise. I do not blame myself for this weakness, because the fault must lie in my physical organization. It is likely that such a very liberal amount of space was given to the organ which enables me to make promises, that the organ which should enable me to keep them was crowded out. But I grieve not. I like no half-way things. I had rather have one faculty nobly developed than two faculties of mere ordinary capacity.”
—Mark Twain [Samuel Langhorne Clemens] (1835–1910)