Yonah (microprocessor) - Technical Specifications

Technical Specifications

Core Duo contains 151 million transistors, including the shared 2 MiB L2 cache. Yonah's execution core contains a 12 stage pipeline, forecast to eventually be able to run at a maximum frequency of 2.33–2.50 GHz. The communication between the L2 cache and both execution cores is handled by a bus unit controller through arbitration, which reduces cache coherency traffic over the FSB, at the expense of raising the core-to-L2 latency from 10 clock cycles (in the Dothan Pentium M) to 14 clock cycles. The increase in clock frequency offsets the impact of the increased clock cycle latency. The power management components of the core features improved grained thermal control, as well as independent scaling of power between the two cores, resulting in very efficient management of power.

Core processors communicate with the system chipset over a 667 MT/s front side bus (FSB), up from 533 MT/s used by the fastest Pentium M. T2050 & T2250 have also appeared in OEM systems as a low-cost option with a lower 533 MHz FSB and no Intel VT-x.

Yonah is supported by the 945GM, 945PM, 945GT, 965GM, 965PM, and 965GT system chipsets. Core Duo and Core Solo use Socket M, but due to pin arrangement and new chipset functions are not compatible with any previous Pentium M motherboard.

The T2300E was later introduced as a replacement for the T2300. It has dropped support for Intel VT-x. Early Intel specifications mistakenly claimed a halving of the Thermal Design Power.