Description
The XS1-G4 comprises four cores and a switch. Each core has a data path, a memory, and register banks for eight threads. Threads running on different cores can communicate with each other by exchanging messages through the switches. Switches of multiple G4s can be connected to form a larger system. The instruction set supports the notion of a channel, a virtual connection between two threads. Channels are supported between threads on a core, between cores on a single chip through a XSwitch, or between cores in the same system if the switches are connected by means of physical links.
Read more about this topic: XCore XS1-G4
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