Features
XAP3, XAP4 and XAP5 are all designed with a load-store RISC architecture that is complemented with multi-cycle instructions for multiplication, division, block copy/store and function entry/exit for maximum efficiency. Cambridge Consultants’ engineers recognised the requirement for these processors to run real-time operating systems capable of handling pre-emptive events and with a fast interrupt response. Consequently the processors are designed with hardware and instruction set support for protected software operating modes that partition user code from privileged operating system and interrupt handler code. The XAP processor hardware manages the mode transitions and call stack in response to events and this approach ensures a fast and deterministic interrupt response. The protected operating modes enable a system on a chip to be designed that is a secure or trustworthy system and offers high availability.
The current XAP processors are designed using the Verilog hardware description language and provided as RTL code ready for logic simulation and logic synthesis with a test bench. They are supported with Cambridge Consultants’ xIDE software development tools and SIF debug technology. These processors and tools enable functional verification and software verification that reduces the project risk, accelerates time-scales and cuts cost of ownership, especially for software engineering.
Read more about this topic: XAP Processor
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