Super Harvard Architecture Single-Chip Computer - The Mercury Multicomputer

The Mercury Multicomputer

Mercury Computer Systems sold a SHARC-based product that used byte addressing. To get this, the compiler was modified to transform addresses. To access memory, the compiler would shift the high 30 bits down by 2 bits. For a load, the compiler would need to rotate the obtained value according to the original low 2 address bits. The compiler would then mask off the higher data bits as needed to obtain the desired 8-bit or 16-bit value. Stores would require loads to be performed so that a masking and merging operation could be performed, much as is done by normal compilers to deal with bit fields. There were some additional complexities related to the desire to avoid low memory addresses (which would allow a NULL pointer to scramble critical motherboard registers) and the desire to avoid this overhead for 32-bit and 64-bit values. Both big-endian and little-endian layouts were possible.

Mercury also implemented 64-bit floating-point in software. They used 40-bit floating-point in the on-chip memory, with interrupts disabled to avoid corrupting the 40-bit registers via storage in 32-bit memory.

Together, these choices allowed Mercury to offer a compiler that would lay out data structures in a way that was fully compatible with their Intel i860 (big-endian) and PowerPC (either big-endian or little-endian) offerings. It was in fact possible to install all three types of CPU in a single shared-memory system, with a distributed OS running on all CPUs.