Quasi Delay Insensitive
In digital logic design, Quasi Delay-Insensitive (QDI) circuits are a class of almost delay-insensitive asynchronous circuits which are invariant to (and make no assumptions about) the delays of any of the circuit's wires or elements, except to assume that certain fanouts are isochronic. Isochronic forks allow signals to travel to two destinations and only receive an acknowledge from one.
More importantly, QDI circuits are Turing-complete, while purely delay-insensitive circuits are not. Of all "useful" asynchronous design styles, QDI circuits make the fewest timing assumptions, as only the isochronic fork is assumed. In practice ensuring the correctness of an isochronic fork is trivial.
Two common design styles of QDI circuits are Delay Insensitive Minterm Synthesis (DIMS) and Pre-Charge Half Buffers based circuits.
Technically, QDI circuits are the same class of circuits as speed-independent circuits. The main difference between speed-independent and QDI circuits is that in QDI circuits, the designer is concerned with the acknowledgment of each transition, whereas in speed-independent design, the correctness of the isochronic assumption on each circuit node is assumed to be true and no distinction is made between circuit nodes that are isochronic forks and those that are not.
Manufactured QDI processor designs include: TITAC from Tokyo Institute of Technology, MiniMIPS from Caltech, SPA from The University of Manchester and ASPRO-216 from France Telecom. The first QDI processor was the Caltech asynchronous microprocessor of 1989 (a predecessor to the MiniMIPS processor).
Read more about Quasi Delay Insensitive: Isochronic Fork
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