Quantum Effect Devices - Devices

Devices

The first QED microprocessor was the R4600. The founders of QED, who were previously involved with the R4000, felt that the large device was too complicated and that a simpler implementation would give a better price/performance ratio. For that reason, the R4600 is a re-implementation of the 5-stage Classic RISC pipeline with large (for the time) caches. For a while, this small and low cost device was one of the highest performance microprocessors on the market. While the initial target market of a MIPS laptop computer never materialized, this device found success in several markets. It was the first RISC processor used within a Cisco Systems network router. It was used in several Atari/Midway arcade games such as the well-known original Mortal Kombat game. The R4600 was licensed by IDT and Toshiba who manufactured and sold the devices.

The R4700 was targeted at SGI, who wanted a little more floating point performance. The R4700 improved on the repeat rate of floating point multiply instructions. This device was used inside the SGI Indy low-end workstation. The R4700 was licensed by IDT and Toshiba who manufactured and sold the devices.

The R4650 was commissioned by NKK, who desired a cheaper implementation for a video console game machine. The R4650 achieved a smaller die area by cutting the caches in half, only implementing single precision floating-point. This device was the first QED device that implemented the multiply–accumulate instructions, which enabled software functions such as softmodem. This device was used in the original Microsoft WebTV device. The R4650 was licensed by IDT and NKK who manufactured and sold the devices. The R4640 was the same chip but with the system bus restricted to 32-bits instead of 64-bits.

The R5000 was commissioned by SGI. This device doubled the instruction and data caches to 32 KB. It implemented a high-performance, fully pipelined floating point unit with multiply–accumulate capability and a SRT divider. The device had a limited implementation of superscalar instruction issue in which one integer instruction and one floating-point instruction could be issued in one cycle. This device was used in the SGI O2 and SGI Indy low-end workstations. The design was owned by SGI, which licensed the design to IDT and NEC and eventually to Toshiba.

The PowerPC 603q was commissioned by Motorola and the target market was Apple Computer's low-cost accounts including a home computer for students and a home video console game named Pippen. The 603q was basically the R4600 pipeline re-targeted for the PowerPC instruction set. Since the PowerPC 603 was then the most power-efficient chip from the AIM alliance, the name of this device was chosen to reflect its low-cost and low-power characteristics. Once those Apple projects were cancelled, Motorola stopped the development of the 603q even though QED had received first silicon samples and they were functional.

The RM52XX series was the first product line sold directly by QED. The first of the series was a cost-reduced version of the R5000 with smaller caches and a different pin-out. The earlier RM52X0 devices had only 16 KB caches while the later RM52X1 devices had 32 KB caches. The RM523X devices had 32-bit system buses while RM526X had 64-bit system buses. This product line was very successful in the laser printer market, winning many accounts at printer companies such as Hewlett-Packard, Lexmark, Ricoh, Samsung.

The RM70XX series was the second product line sold directly by QED. It implemented a large 256 KB on-chip level 2 cache. The RM7000 was one of the first microprocessors to do so, especially within the embedded microprocessor market segment. It also implemented symmetric superscalar instruction issue with two integer execution units. The RM7061 device was a pin-compatible upgrade for the RM526X series. This product line was a very successful follow-on to the RM52XX products.

The RM9x00 family was the first SOC implemented by QED. The Apollo microprocessor core that was part of the RM9x00 had its pipeline lengthened to 7 stages to enable higher operating frequencies. Dynamic branch prediction was added to ameliorate the longer branch latencies. Within the RM9x00, two Apollo cores were used to implement a dual-core device. These processor cores successfully achieved their operating frequency target of 1 GHz. The SOC system interconnect was an in-house design with centralized storage for the transactions flowing through the SOC. Peripherals included a DDR memory controller, a SysAD bus controller, a boot bus controller, a DMA controller and a Hypertransport controller. A second generation device added a Gigabit ethernet controller, a PCI controller and cache coherency. This product family was not successful due to being late to the market. The company was financially conservative during the time leading up to and after the company's initial public offering and would not fully staff the SOC project. One of the reasons for selling the company to PMC-Sierra was to fund these SOC projects. By that time, competitors like SiByte had already entered the market with equivalent devices.