PIO Mode in The ATA Interface
Until the introduction of DMA, PIO was the only available method.
The PIO interface is grouped into different modes that correspond to different transfer rates. The electrical signaling among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.
The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually UDMA) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are not required like in embedded systems, or with FPGA chips where PIO mode can be used without significant performance loss.
Two additional Advanced Timing modes have been defined in the CompactFlash specification 2.0. Those are PIO mode 5 and PIO mode 6. They are specific to CompactFlash.
| Mode | Maximum transfer rate (MB/s) | Minimum cycle time | Standard where spec is defined |
|---|---|---|---|
| Mode 0 | 3.3 | 600 ns | ATA-1 |
| Mode 1 | 5.2 | 383 ns | ATA-1 |
| Mode 2 | 8.3 | 240 ns | ATA-1 |
| Mode 3 | 11.1 | 180 ns | ATA-2 |
| Mode 4 | 16.7 | 120 ns | ATA-2 |
| Mode 5 | 20 | 100 ns | CompactFlash 2.0 |
| Mode 6 | 25 | 80 ns | CompactFlash 2.0 |
Read more about this topic: Programmed Input/output
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