Power Architecture - Description

Description

The instruction set architecture is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.

Power is a RISC load/store architecture. It has multiple sets of registers:

• thirty-two 32-bit or 64-bit general purpose registers (GPRs) for integer operations.
• sixty-four 128-bit vector scalar registers (VSRs) for vector operations and floating point operations.
  • thirty-two 64-bit floating-point registers (FPRs) as part of the VSRs for floating point operations.
  • thirty-two 128-bit vector registers (VRs) as part of the VSRs for vector operations.
• Eight 4-bit condition register fields (CRs) for comparison and flow control.
• Special registers: counter register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).

Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.

Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianess. Support for both 32-bit and 64-bit addressing.

Different modes of operation: User, supervisor and hypervisor.