Description
| Designer | Power.org |
|---|---|
| Bits | 32-bit/64-bit (32 → 64) |
| Introduced | 2006 |
| Version | 2.06 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed/Variable |
| Branching | Condition code |
| Endianness | Big/Bi |
| Extensions | AltiVec, APU, DSP, CBEA |
| Open | Yes |
| Registers | |
|
|
The instruction set architecture is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.
Power is a RISC load/store architecture. It has multiple sets of registers:
- thirty-two 32-bit or 64-bit general purpose registers (GPRs) for integer operations.
- sixty-four 128-bit vector scalar registers (VSRs) for vector operations and floating point operations.
- thirty-two 64-bit floating-point registers (FPRs) as part of the VSRs for floating point operations.
- thirty-two 128-bit vector registers (VRs) as part of the VSRs for vector operations.
- Eight 4-bit condition register fields (CRs) for comparison and flow control.
- Special registers: counter register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).
Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.
Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianess. Support for both 32-bit and 64-bit addressing.
Different modes of operation: User, supervisor and hypervisor.
Read more about this topic: Power Architecture
Famous quotes containing the word description:
“The great object in life is Sensation—to feel that we exist, even though in pain; it is this “craving void” which drives us to gaming, to battle, to travel, to intemperate but keenly felt pursuits of every description whose principal attraction is the agitation inseparable from their accomplishment.”
—George Gordon Noel Byron (1788–1824)
“Everything to which we concede existence is a posit from the standpoint of a description of the theory-building process, and simultaneously real from the standpoint of the theory that is being built. Nor let us look down on the standpoint of the theory as make-believe; for we can never do better than occupy the standpoint of some theory or other, the best we can muster at the time.”
—Willard Van Orman Quine (b. 1908)
“A sound mind in a sound body, is a short, but full description of a happy state in this World: he that has these two, has little more to wish for; and he that wants either of them, will be little the better for anything else.”
—John Locke (1632–1704)