PCI Configuration Space - Hardware Implementation

Hardware Implementation

When performing a configuration space access, a PCI device does not decode the address to determine if it should respond, but instead looks at the signal IDSEL. There is a system-wide unique activation method for each IDSEL signal. The IDSEL is different for each PCI device/adapter slot. Further, the device is required to decode only the lowest order 11 bits of the address space (AD to AD) address/data signals, and can ignore the high order 21 A/D signals ( – AD) completely.

Thus typically, an implementation has each slot's IDSEL pin connected to a different address/data line AD through AD. To configure the card in slot n, the PCI bus bridge performs a configuration-space access cycle with the PCI device's register to be addressed on lines AD (AD are always zero since registers are double words (32-bits)), and the PCI function number specified on bits AD, with all higher-order bits zeros except for AD being used as the IDSEL signal on a given slot.

To reduce electrical loading on the timing critical (and thus loading sensitive) AD bus, usually the IDSEL signal on the slot connector is connected to an AD through a resistor. This causes the IDSEL signal to get to its active condition more slowly than other PCI bus signals (due to the RC time constant of the resistor and the IDSEL pin's input capacitance), so configuration space accesses are performed more slowly to allow time for the IDSEL signal to reach a valid level.

The scanning on the bus is performed on the Intel platform by accessing two defined standardized ports. These ports are the Configuration Space Address (0xCF8) I/O port and Configuration Space Data (0xCFC) I/O port. The value written to the Configuration Space Address I/O port is created by combining D/B/F values and the registers address value into a 32-bit word.