Original Chip Set - Agnus

Agnus

The Agnus chip is in overall control of the entire chipset's operation. All operations are synchronised with the output of the video beam. This includes access to the built-in RAM, known as chip RAM because the chipset has access to it. Both the central 68000 processor and other members of the chipset have to arbitrate for access to RAM via Agnus. In computing architecture terms, this is Direct Memory Access (DMA), where Agnus is the DMA Controller (DMAC).

Agnus has a complex priority-based memory access policy. For example, bitplane data fetches are prioritized over blitter transfers. As the original 68000 processor in Amigas tended only to access memory on every second available memory cycle, Agnus operated a system where the time-critical custom chips access got the "odd" clock cycle and the CPU got the "even" cycle, thus the CPU did not generally get locked out of memory access and did not appear to slow down. However, non-time-critical custom chip access, such as blitter transfers, can use up any spare odd or even cycles and, if the "BLITHOG" (blitter hog) flag is set, Agnus can lock out the even cycles from the CPU in deference to the blitter.

Agnus's timings are measured in "colour clocks" of 280 ns. This is equivalent to two low resolution (140 ns) pixels or four high resolution (70 ns) pixels. Like Denise, these timings were designed for display on household TVs, and can be synchronised to an external clock source.