Phase Accumulator
A binary phase accumulator consists of an N-bit binary adder and a register configured as shown in Figure 1. Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size, the integer value of the FCW. In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle latency but allows the adder to operate at a higher clock rate.
The adder is designed to overflow when the sum of the absolute value of its operands exceeds its capacity (2N−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder, called the residual, is stored in the register and the cycle repeats, starting this time from (see figure 2). Since a phase accumulator is a finite state machine, eventually the residual at some sample K must return to the initial value . The interval K is referred to as the grand repetition rate (GRR) given by
where GCD is the greatest common divisor function. The GRR represents the true periodicity for a given which for a high resolution NCO can be very long. Usually we are more interested in the operating frequency determined by the average overflow rate, given by
- (1)
The frequency resolution, defined as the smallest possible incremental change in frequency, is given by
- (2)
Equation (1) shows that the phase accumulator can be thought of as a programmable non-integer frequency divider of divide ratio .
Read more about this topic: Numerically Controlled Oscillator
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