Motorola 68060 - Architecture

Architecture

For more information on the instruction set and architecture, see Motorola 68000.

There is an LC (Low-Cost) version, without an FPU and EC (Embedded Controller), without MMU and FPU. The 68060 design was led by Joe Circello.

The 68060 shares most architectural features with the P5 Pentium. Both have a very similar superscalar in-order dual instruction pipeline configuration, and an instruction decoder which breaks down complex instructions into simpler ones before execution. However, a significant difference is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications. In contrast to that, integer multiplications and bit shifting instructions are significantly faster on the 68060. An interesting feature of the 68060 is the ability to execute simple instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU. Another point of interest is that large amounts of commercial compiled code were analyzed for clues as to which instructions would be the best candidates for performance optimization.

Against the Pentium, the 68060 could perform better on mixed code, Pentium's decoder could not issue an FP instruction every opportunity and hence the FPU was not superscalar as the ALUs were. If the 68060's non-pipelined FPU could accept an instruction, it could be issued one by the decoder. This meant that optimizing for the 68060 was easier, no rules prevented FP instructions from being issued whenever was convenient for the programmer other than well understood instruction latencies. However, with properly optimized and scheduled code, the Pentium's FPU was capable of double the clock for clock throughput of the 68060's FPU.

The 68060 was the last development of the 680x0 series for general purpose use, abandoned in favor of the PowerPC chips. It saw use in some late-model Amiga machines and Amiga accelerator cards as well as some Atari ST clones and a Falcon accelerator board (CT060), and very late models of the Alpha Microsystems multiuser computers before their migration to x86, but Apple Inc. and the Unix world had moved onto various RISC platforms by the time the '060 was available. The 68060 was introduced at 50 MHz on Motorola's 0.6 µm manufacturing process. A few years later it was shrunk to 0.42 µm and clock speed raised to 66 MHz and 75 MHz.

Developments of the basic core continue, intended for embedded systems. Here they are combined with a number of peripheral interfaces to reduce the overall complexity and power requirements of a design. A number of chips, each with different sets of interfaces, are sold under the name ColdFire and DragonBall.