Motorola 68000 Family - Improvement Roadmap

Improvement Roadmap

68010

• Virtual memory support (restartable instructions).
• 'loop mode' for faster string and memory library primitives.

68020

• 32-bit address & ALU.
• 3 stage pipeline.
• Instruction cache of 256 bytes.
• Unrestricted word and longword data access (see alignment).
• 8 x multiprocessing capability.
• Larger multiply (32×32 -> 64 bits) and divide (64÷32 -> 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.
• Addressing modes added scaled indexing and another level of indirection.
• Low cost, EC = 24-bit address.

68030:

• Split instruction and data cache of 256 bytes each
• On-chip MMU (68851).
• Low cost EC = No MMU.

68040:

• Instruction and data caches of 4 kilobytes each
• 6 stage pipeline.
• FPU lacks IEEE transcendental functions capability.
• FPU emulation works with 2E71M and later chip revisions.
• Low cost LC = No FPU.
• Low cost EC = No FPU & MMU.

68060:

• Instruction and data caches of 8 kilobytes each
• 10 stage pipeline.
• Two cycle integer multiplication unit.
• Branch prediction.
• Dual instruction pipeline.
• Instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU.
• Low cost LC = No MMU.
• Low cost EC = No MMU & FPU.