Motorola 6800 - MOS ICs

MOS ICs

The first generation metal-oxide semiconductors used p-channel field effect transistors, known as a p-channel MOSFET. (P-channel describes the configuration of the transistor.) These ICs were used in calculators and the first microprocessor, the Intel 4004. They were easy to produce but were slow and difficult to interface to the popular TTL digital logic ICs. An n-channel MOS integrated circuit could operate two or three times faster and was compatible with TTL. They were much more difficult to produce because of an increased sensitivity to contamination that required an ultra clean production line and meticulous process control. Motorola did not have an n-channel MOS production capability and had to develop one for the 6800 family.

Motorola's n-channel MOS test integrated circuits were complete in late 1971 and these indicated the clock rate would be limited to 1 MHz. These used "enhancement-mode" MOS transistors. There was a newer fabrication technology that used "depletion-mode" MOS transistors that would allow smaller and faster circuits. (This was also known as "depletion-load".) The "depletion-mode" processing required extra steps so Motorola decided to stay with "enhancement-mode" for the new single supply voltage design. The 1 MHz clock rate meant the chip designers would have to come up with several architectural innovations to speed up the microprocessor throughput. These resulting circuits were faster but required more area on the chip.

In the 1970s, semiconductors were fabricated on 3 inch (75 mm) diameter silicon wafers. Each wafer could produce 100 to 200 integrated circuit chips or dies. The technical literature would state the length and width of each chip in "mils" (0.001 inch). The Intel 8080 microprocessor chip size was 164 mils x 191 mils (4.1 mm by 4.9 mm). The current industry practice is to state the chip area so the size of the 8080 chip would be 19.7 mm2.

Processing wafers required multiple steps and flaws would appear at various locations on the wafer during each step. The larger the chip the more likely it would encounter a defect. The percentage of working chips or yield began to decline for chips larger than 160 mils (4 mm) on a side. The target size for the 6800 was 180 mils (4.6 mm) on each side but the final size was 212 mils (5.4 mm ) with an area of (29.0 mm2). At 180 mils, a 3-inch (76 mm) wafer will hold about 190 chips, 212 mils reduces that to 140 chips. At this size the yield may be 20% or 28 chips per wafer. The Motorola 1975 annual report highlights the new MC6800 microprocessor but has several paragraphs on the "MOS yield problems." The yield problem was solved with design revision started in 1975 to use depletion mode in the M6800 family devices. The 6800 die size was reduced to 160 mils (4 mm) per side with an area of 16.5 mm2. This also allowed faster clock speeds, the MC68A00 would operate at 1.5 MHZ and the MC68B00 at 2.0 MHz. The new parts were available in July 1976.