Detailed Behavior
The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that the interrupt is triggered by the falling edge of the signal rather than its level.
The simultaneous assertion of the NMI (non-maskable) and IRQ (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will immediately respond to IRQ, as IRQ is level sensitive. Thus a sort of built-in interrupt priority was established in the 6502 design.
The "Break" flag of the processor is very different from the other flag bits. It has no flag setting, resetting, and testing instructions of its own, and is not handled by the PHP and PLP instructions either. It exists only on the stack, where BRK and PHP always write a 1, while IRQ and NMI always write a 0.
The "SO" input pin, when asserted, would set the processor's overflow status bit (deasserting it does not clear the overflow bit, however). This can be used by a high-speed polling device driver, which can poll the hardware once in only three cycles by using a Branch-on-oVerflow-Clear (BVC) instruction that branches to itself; for example the Commodore 1541 and other Commodore floppy disk drives use it to detect as quickly as possible whether the serializer is ready to accept or provide another byte of disk data, as a normal test-and-branch loop takes seven cycles which is too slow in that particular application. Obviously great care must be used in the device driver and the associated system design, as spurious assertion of the overflow bit could ruin arithmetic processing.
Read more about this topic: MOS Technology 6502
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