MMX (instruction Set) - Successor

Successor

AMD, a competing x86 microprocessor vendor, enhanced Intel's MMX with their own 3DNow! instruction set. 3DNow is best known for adding single-precision (32-bit) floating-point support to the SIMD instruction-set, among other integer and more general enhancements.

Following MMX, Intel's next major x86 extension was the SSE, introduced with the Pentium-III family (roughly a year after AMD's 3DNow! was introduced.)

SSE addressed the core shortcomings of MMX (inability to mix integer-SIMD ops with any floating-point ops) by creating a new 128-bit wide register file (XMM0 - XMM7) and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations (32-bit); integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops.

SSE2, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer (8/16/32 bit) and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMX opcodes to use XMM register operands, but ended this support with SSE4 (and recently with SSE4.2, introduced in the Core microarchitecture.) However, since processor support for any SSE revision also implies support for MMX, the removal does not limit the types of data types usable by x86 SIMD.