Memory bank is a part of (cache) memory that is addressed consecutively in the total set of memory banks, i.e., when data item a(n) is stored in bank b, data item a(n + 1) is stored in bank b + 1. (Cache) memory is divided in banks to evade the effects of the bank cycle time (see above). When data is stored or retrieved consecutively each bank has enough time to recover before the next request for that bank arrives.
The number of memory modules needed to have the same number of data bits as the bus. A bank can consist of one or more memory modules.
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