Memory Bandwidth - Computation

Computation

Theoretical maximum memory bandwidth is typically computed by multiplying the width of the interface by the frequency at which it transfers data. This is also referred to as the burst rate of the interface, in recognition of the possibility that this rate may not be sustainable over long periods (i.e., the throughput may be less than the theoretical maximum memory bandwidth).

The nomenclature standards often differ across memory technologies, but for commodity DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM memory the computation is:

• Base DRAM frequency in MHz (millions of DRAM clock cycles per second).
• Memory interface (or bus) width. Each standard DDR, DDR2, or DDR3 memory interface is 64 bits (8 bytes) wide. (The width is sometimes referred to in lines or lanes, rather than bits, though these are synonymous here.)
• Number of interfaces. Current computers typically use two memory interfaces in dual-channel mode for an effective 128-bit width.
• Number of bits per clock cycle per line. This is 2 for DDR, DDR2, and DDR3 dual data rate technologies.

So a recent computer system with a dual-channel configuration and two DDR2-800 modules, each running at 400 MHz (actual bus speed, which is half of the nominal speed of 800 MHz, but in DDR2 is twice the memory's actual clock of 400 MHz), would have a theoretical maximum memory bandwidth of:

• (400 million hertz * (2 interfaces) * (64 lines/interface) * (2 bits/line-cycle)) = 102,400 Mbit/s, or 12,800 MB/s, or 12.8 GB/s.

The naming conventions of DDR, DDR2 and DDR3 modules typically cite a nominal MHz rating (e.g., DDR2-1066) which is not the bus speed or memory speed, but the number of transfers possible per second, and an additional nominal rating of the maximum throughput of the module (e.g., DDR2-800 is also called PC2-6400) which reflects the theoretical maximum bandwidth in megabytes per second. So with this in mind, the above computation can be simplified as having two PC2-6400 modules in a dual-channel 128-bit configuration, or 2 × 6,400 MiB/s.

The choice of two memory interfaces in the above example is a common configuration, but single-channel configurations are common in low-end and low-power devices, and more than two channels are used in some high-performance systems. As of 2007, advanced personal computers and graphics cards use even more combined buses than dual-channel, and combine four (e.g., Mac Pro), five (e.g., nVidia 8800GTS), six (e.g., nVidia 8800GTX), or more sets of 64-bit memory modules and buses to reach 256-bit, 320-bit, 384-bit or greater total memory bus width. In this sort of multi-channel configuration, memory must be broken out so that there is at least one 64-bit wide chip or module for each channel. So for a 256-bit wide 4 GiB configuration with DDR2 modules, one must have 4×1 GiB modules (or 8x512 MiB, 16x256 MiB, etc.) since each of these standard modules provides only a 64-bit interface.

Note that in systems with error-correcting memory, the additional width of the interfaces (typically 72 bits rather than 64 bits) is not counted in the bandwidth computations, as neither the extra memory nor the extra bandwidth is available for user data.