Low-voltage Differential Signaling - Differential Vs. Single-ended Signaling

Differential Vs. Single-ended Signaling

LVDS is a differential signaling system, meaning that it transmits information as the difference between the voltages on a pair of wires; the two wire voltages are compared at the receiver. In a typical implementation, the transmitter injects a constant current of 3.5 mA into the wires, with the direction of current determining the digital logic level. The current passes through a termination resistor of about 100 to 120 ohms (matched to the cable’s characteristic impedance to reduce reflections) at the receiving end, and then returns in the opposite direction via the other wire. From Ohm's law, the voltage difference across the resistor is therefore about 350 mV. The receiver senses the polarity of this voltage to determine the logic level.

As long as there is tight electric- and magnetic-field coupling between the two wires, LVDS reduces the generation of electromagnetic noise. This noise reduction is due to the equal and opposite current flow in the two wires creating equal and opposite electromagnetic fields that tend to cancel each other. In addition, the tightly coupled transmission wires will reduce susceptibility to electromagnetic noise interference because the noise will equally affect each wire and appear as a common-mode noise. The LVDS receiver is unaffected by common mode noise because it senses the differential voltage, which is not affected by common mode voltage changes.

The low common-mode voltage (the average of the voltages on the two wires) of about 1.2V allows using LVDS with a wide range of integrated circuits with power supply voltages down to 2.5V or lower. In addition, there are variations of LVDS that use a lower common mode voltage. One example is sub-LVDS (introduced by Nokia in 2004) that uses 0.9V typical common mode voltage. Another is Scalable Low Voltage Signaling for 400 mV (SLVS-400) specified in JEDEC JESD8-13 October 2001 where the power supply can be as low as 800 mV and common mode voltage is about 400 mV.

The low differential voltage, about 350 mV, causes LVDS to consume very little power compared to other signaling technologies. At 2.5V supply voltage the power to drive 3.5 mA becomes 8.75 mW, compared to the 90 mW dissipated by the load resistor for an RS-422 signal.

Logic Levels:

LVDS is not the only differential signaling system in use, but is currently the only scheme that combines low power dissipation with high speed.