The Fetch-Execute Cycle in Transfer Notation
Expressed in register transfer notation:
(Increment the PC for next cycle at the same time)
The registers used above, besides the ones described earlier, are the Memory Address Register (MAR) and the Memory Data Register (MDR), which are used (at least conceptually) in the accessing of memory. Often, the MDR is expressed as the MBR (Memory Buffer Register).
Fetch and execute example (written in RTL - Register Transfer Language):
PC=0x5AF, AC=0x7EC3, M=0x932E, M=0x09AC, M=0x8B9F.
T0 : AR = 0x5AF (PC)
T1 : IR = 0x932E (M), PC=0x5BO
T2 : DECODE = ADD opCode 0x932E, AR=0x32E, I=1. (Indirect instruction)
T3 : AR = 0x9AC (M)
T4 : DR = 0x8B9F
T5 : AC = 0x8B9F + 0x7EC3 = 0x0A62, E = 1 (carry out), SC = 0
Summary: this example is for an ADD Instruction which made Indirect where:
T0-T1 is the Fetch operation.
T2 is the operation code Decode.
T3 Indirect Memory reference
T4-T5 Execute ADD operation
Read more about this topic: Instruction Cycle
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