Immersion Lithography - Future of Immersion Lithography

Future of Immersion Lithography

As of 2007, many companies, including IBM, UMC, Toshiba, and TI are ramping for the 45 nm node using immersion lithography. AMD's Fab 36 is already equipped for using immersion lithography for its 65 nm, 45 nm and 32 nm node technologies. AMD has also made preparations for advanced design for manufacturability (DFM), including layout regularity and double patterning at the 22 nm node, using immersion lithography. For the 32 nm node in 2009, Intel will begin using immersion lithography as well. Intel has confirmed that since EUV will not be available, it will extend 193 nm immersion lithography to the 22 nm node and 15 nm node. Intel has already outlined a path to use 193 nm immersion lithography down to 11 nm node. IBM has also stated that it will be using immersion lithography for the 22 nm node, since no other alternative is available at this time.

Enhancements necessary to extend the technology beyond the 32 nm node are currently being investigated. Such enhancements include the use of higher refractive-index materials in the final lens, immersion fluid, and photoresist, in order to improve the resolution with single patterning.

Currently, the most promising high-index lens material is lutetium aluminum garnet, with a refractive index of 2.14. High-index immersion fluids are approaching refractive index values of 1.7. These new developments allow the optical resolution to approach ~30 nm. However, it is expected that at some point below 40 nm, current photoresists will limit further scaling. Polarization effects due to high angles of interference in the photoresist also have to be considered as features approach 40 nm. Hence, new photoresists will need to be developed for sub-40 nm applications.

On the other hand, double patterning has received interest recently since it can potentially increase the half-pitch resolution by a factor of 2. This could allow the use of immersion lithography tools beyond the 32 nm node, potentially to the 16 nm node. While double patterning improves pitch resolution, it must rely on non-lithographic methods, such as trimming, to actually reduce the feature size, possibly by as much as 50%.

On March 23, 2012, with the release of the Ivy Bridge chip, Intel's Senior Fellow Mark Bohr stated that the company will be able to extend its current immersion process to the 14-nm and even 10-nm chips before EUV would be necessary. He did not mention specific techniques that will be utilized.