2100 Series Architecture
There were two 16-bit accumulators, called A and B which could do most instructions such as load or add, and two 1-bit flags, called Overflow and Extend, although the A register had a few more instructions. The program counter, 15 bits, was called P. All instructions in the standard instruction set were 16 bits long. The earlier PDP-8 from DEC had just one accumulator and a 12-bit address. Memory was word accessible, unlike the later PDP-11, which was addressable by byte. Conditional branching was done with a conditional skip followed by a jump instruction. There was no dedicated stack register.
The processor instruction-set architecture was very efficient, predating RISC architectures with some similar features 20 years later, as there were only 68 instructions. All instructions are fixed width, 16 bits wide, and all instructions executed in one memory cycle (1.6 microseconds). However, instructions could address both memory and a register, it had only two accumulators instead of a series of general registers (such as the PDP-11). The register-reference instructions could execute multiple operations per instruction (RISC processors generally execute only one operation per instruction)
The smallest addressable unit of memory was a 16-bit word, and the maximum possible address was 32,767, which would fit in a word with one bit left over. The most significant bit of any memory-reference instruction indicated indirect addressing: The word addressed by the instruction, instead of being the operand, contained the operand address. In early members of the series the most significant bit of that word could be set to indicate an additional level of indirect addressing, and this could be iterated any number of times.
With no stack for saving procedure return points, indirect addressing was used to implement procedure call and return: The first word of a procedure was reserved for the return address, and the jump to subroutine instruction would store the return address there. The return to caller was performed via a jump indirect through that word. This design also appeared in other machines of the era, such as the CDC 3000 series.
The early machines in the series (including the 2116) were direct-execution machines but the 2100 and later machines were microprogrammed. The 2100 offered a writable control store allowing the user to extend and change the vertical microcode.
The 2100-series of processors is one of the systems on which the SIMH multi-system emulator is able to run.
Read more about this topic: HP 2100
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