Hardware Description Language - History

History

The first hardware description languages appear in the late 1960s looking like more traditional languages. The first that had a lasting effect was described in 1971 in C. Gordon Bell and Allen Newell's text Computer Structures. It was this text where the concept of RTL was introduced in the ISP language to describe the behavior of the DEC PDP-8.

The language became more wide spread with the introduction of Digital Equipment Corporation (DEC) PDP-16 RT-Level Modules and a book describing their use. At least two implementations of the basic ISP language (ISPL and ISPS) followed. ISPS was well suited to describe relations between the inputs and the outputs of the design and quickly became adopted by commercial teams at DEC, as well as a number of research teams both in the USA and in NATO allies. However, the ability to synthesize logic turned out to be limited, as the simulator output assumed that the design would be reduced to practice using those same DEC RTM style PDP-16 modules. The RTM's product never really took off commercially and DEC stopped marketing them in the mid-1980s, as new techniques and in particular VLSI became more popular.

Separate work circa 1979 at University of Kaiserslautern produced a language called KARL, which included design calculus language features supporting VLSI chip floorplanning and structured hardware design. The same work was also the basis of KARL's interactive graphic sister language ABL, implemented in the early 1980s as the ABLED graphic VLSI design editor, by the telecommunication research center CSELT at Torino, Italy. In the mid 1980s, a VLSI design framework was implemented around KARL and ABL by an international consortium funded by the commission of the European Union (chapter in ).

By the late 1970s, design using programmable logic device (PLD)'s became popular, although these designs were primarily limited to design finite state machines. The work at Data General in 1980 used these same devices to design a then modern system, the Data General Eclipse MV/8000, and commercial need began to grow for a language that could map to well to them. By 1983 Data-I/O introduced ABEL, to fill that need.

As design shifted to VLSI, the first modern HDL, Verilog, was introduced by Gateway Design Automation in 1985. Cadence Design Systems later acquired the rights to Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog simulators) for the next decade. In 1987, a request from the U.S. Department of Defense led to the development of VHDL (VHSIC Hardware Description Language, where VHSIC is Very High Speed Integrated Circuit). VHDL was based on the Ada programming language, as well as the experiences that had been learned with the development of ISPS earlier. Initially, Verilog and VHDL were used to document and simulate circuit designs already captured and described in another form (such as schematic files). HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands.

The introduction of logic synthesis for HDLs pushed HDLs from the background into the foreground of digital design. Synthesis tools compiled HDL source files (written in a constrained format called RTL into a manufacturable gate/transistor-level netlist description. Writing synthesizable RTL files required practice and discipline on the part of the designer; compared to a traditional schematic layout, synthesized RTL netlists were almost always larger in area and slower in performance. A circuit design from a skilled engineer, using labor-intensive schematic-capture/hand-layout, would almost always outperform its logically-synthesized equivalent, but the productivity advantage held by synthesis soon displaced digital schematic capture to exactly those areas that were problematic for RTL synthesis: extremely high-speed, low-power, or asynchronous circuitry. In short, logic synthesis propelled HDL technology into a central role for digital design.

Within a few years, both VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared from use. However, VHDL and Verilog share many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit simulation. Neither possesses language constructs to describe recursively-generated logic structures. Specialized HDLs (such as Confluence) were introduced with the explicit goal of fixing specific Verilog/VHDL limitations, though none were ever intended to replace VHDL/Verilog.

Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for better testbench randomization, design hierarchy, and reuse. A future revision of VHDL is also in development, and is expected to match SystemVerilog's improvements.