Front-side Bus - Transfer Rates

Transfer Rates

The bandwidth or maximum theoretical throughput of the front-side bus is determined by the product of the width of its data path, its clock frequency (cycles per second) and the number of data transfers it performs per clock cycle. For example, a 64-bit (8-byte) wide FSB operating at a frequency of 100 MHz that performs 4 transfers per cycle has a bandwidth of 3200 megabytes per second (MB/s):

8 B × 100 MHz × 4/cycle = 3200 MB/s

The number of transfers per clock cycle depends on the technology used. For example, GTL+ performs 1 transfer/cycle, EV6 2 transfers/cycle, and AGTL+ 4 transfers/cycle. Intel calls the technique of four transfers per cycle Quad Pumping.

Many manufacturers publish the speed of the FSB in MHz, but often do not use the actual physical clock frequency but the theoretical effective data rate (which is commonly called megatransfers per second or MT/s). This is because the actual speed is determined by how many transfers can be performed by each clock cycle as well as by the clock frequency. For example, if a motherboard (or processor) has an FSB clocked at 200 MHz and performs 4 transfers per clock cycle, the FSB is rated at 800 MT/s.