Flat Memory Model - Von Neumann Vs. Harvard Architectures

Von Neumann Vs. Harvard Architectures

Finally, there seems to be some confusion regarding the relationship between a flat memory model and Von Neumann vs Harvard architectures.

A Von Neumann architecture specifies that instructions and data are both stored within the same memory and transferred over the same bus. This type of architecture is the most space efficient, because any memory not used by the program is available for data and vice versa. It is most often used in general computing.

A Harvard architecture, on the other hand, separates instructions and data into two separate memories which are typically accessed over two separate buses. The benefit is an increase in system performance because data (for the present instruction) and code (for the future instruction) can be fetched at the same time. Also, in a Harvard architecture, the instruction and data buses can have different speeds and geometries. The drawback is that Harvard architectures force the designer to make assumptions about the ratio of instruction vs data memory, and this memory cannot be re-allocated at run time. The system is therefore unavoidably more wasteful. This type of architecture is most often used in digital signal processing (DSP), real-time control and ultra high-speed RISC applications, where performance is of utmost importance and everything else is secondary.

The point is that neither of the above architectures makes any claims whether the memory addressing model is flat, segmented, paged or otherwise.