Explicitly Parallel Instruction Computing - Roots in VLIW

Roots in VLIW

By 1989, researchers at HP recognized that RISC architectures were reaching a limit at one instruction per cycle. They began an investigation into a new architecture, later named EPIC. The basis for the research was VLIW, in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the software compiler, which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploit instruction level parallelism (ILP), by using the compiler to find and exploit additional opportunities for parallel execution.

VLIW (at least the original forms) has several short-comings that precluded it from becoming mainstream:

• VLIW instruction sets are not backward compatible between implementations. When wider implementations (more execution units) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
• Load responses from a memory hierarchy which includes CPU caches and DRAM do not have a deterministic delay. This makes static scheduling of load instructions by the compiler very difficult.

EPIC architecture has evolved from VLIW architecture, while retaining many concepts of the superscalar architecture.