Moving Beyond VLIW
EPIC architectures add several features to get around the deficiencies of VLIW:
- Each group of multiple software instructions is called a bundle. Each of the bundles has a stop bit indicating if this set of operations is depended upon by the subsequent bundle. With this capability, future implementations can be built to issue multiple bundles in parallel. The dependency information is calculated by the compiler, so the hardware does not have to perform operand dependency checking.
- A software prefetch instruction is used as a type of data prefetch. This prefetch increases the chances for a cache hit for loads, and can indicate the degree of temporal locality needed in various levels of the cache.
- A speculative load instruction is used to speculatively load data before it is known whether it will be used (bypassing control dependencies), or whether it will be modified before it is used (bypassing data dependencies).
- A check load instruction aids speculative loads by checking whether a speculative load was dependent on a later store, and thus must be reloaded.
The EPIC architecture also includes a grab-bag of architectural concepts to increase ILP:
- Predicated execution is used to decrease the occurrence of branches and to increase the speculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.
- Delayed exceptions, using a not a thing bit within the general purpose registers, allow speculative execution past possible exceptions.
- Very large architectural register files avoid the need for register renaming.
- Multi-way branch instructions improve branch prediction by combining many alternative branches into one bundle.
The Itanium architecture also added register renaming and rotating register files, a tool useful for software pipelining since it avoids having to manually unroll and rename registers.
Read more about this topic: Explicitly Parallel Instruction Computing
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