Effect On Memory Access Speed
With asynchronous DRAM, the time delay between presenting a column address and receiving the data on the output pins is constant. Synchronous DRAM, however, has a CAS latency which is dependent upon the clock rate. Accordingly, the CAS latency of an SDRAM memory module is specified in clock ticks instead of real time.
Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the data to be read is known long enough in advance; if the data being accessed is not predictable, pipeline stalls can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.
In general, the lower the CAS latency, the better. Because modern DRAM modules' CAS latencies are specified in clock ticks instead of time, when comparing latencies at different clock speeds, latencies must be translated into actual times to make a fair comparison; a higher numerical CAS latency may still be a shorter real-time latency if the clock is faster. However, it is important to note that the manufacturer-specified CAS latency typically assumes the specified clock rate, so underclocking a memory module may also allow for a lower CAS latency to be set.
Double data rate RAM operates using two transfers per clock cycle. The transfer rate is typically quoted by manufacturers, instead of the clock rate, which is half of the transfer rate for DDR modules. Because the CAS latency is specified in clock cycles, and not transfer ticks (which occur on both the positive and negative edge of the clock), it is important to ensure it is the clock rate which is being used to compute CAS latency times, and not the doubled transfer rate.
Another complicating factor is the use of burst transfers. A modern microprocessor might have a cache line size of 64 bytes, requiring eight transfers from a 64-bit-wide (8 bytes) memory to fill. The CAS latency can only accurately measure the time to transfer the first word of memory; the time to transfer all eight words depends on the data transfer rate as well. Fortunately, the processor typically does not need to wait for all eight words; the burst is usually sent in critical word first order, and the first critical word can be used by the microprocessor immediately.
In the table below, data rates are given in million transfers—also known as Megatransfers—per second (MT/s), while clock rates are given in MHz, million cycles per second.
Read more about this topic: CAS Latency
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