Example: Fujitsu 65 Nm Process
- Gate length: 30 nm (high-performance) to 50 nm (low-power)
- Core voltage: 1.0 V
- 11 Cu interconnect layers using nano-clustering silica as ultralow k dielectric (k=2.25)
- Metal 1 pitch: 180 nm
- Nickel silicide source/drain
- Gate oxide thickness: 1.9 nm (n), 2.1 nm (p)
There are actually two versions of the process: CS200, focusing on high performance, and CS200A, focusing on low power.
Read more about this topic: 65 Nanometer
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“That which endures is not one or another association of living forms, but the process of which the cosmos is the product, and of which these are among the transitory expressions.”
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