65 Nanometer - Example: Fujitsu 65 Nm Process

Example: Fujitsu 65 Nm Process

• Gate length: 30 nm (high-performance) to 50 nm (low-power)
• Core voltage: 1.0 V
• 11 Cu interconnect layers using nano-clustering silica as ultralow k dielectric (k=2.25)
• Metal 1 pitch: 180 nm
• Nickel silicide source/drain
• Gate oxide thickness: 1.9 nm (n), 2.1 nm (p)

There are actually two versions of the process: CS200, focusing on high performance, and CS200A, focusing on low power.