64b/66b Encoding - Properties and Application

Properties and Application

64b/66b's design goals are clock recovery, stream alignment, DC balance, transition density and run length. Unlike 8b/10b which guarantees strict bounds on DC balance, transition density and run length, 64b/66b provides statistical bounds on these properties. Although it is theoretically possible for a specific data pattern to align with the scrambler state and produce a long run of 65 zeroes or 65 ones, the probability of such an event is equal to flipping an unbalanced coin and having it come up in the same state 65 times in a row. At 10 Gigabits per second, the expected time for a 64 bit run-length to occur is 265/109 seconds, or about once every 58 years. Most clock recovery circuits designed for SONET OC-192 and 64b/66b are specified to tolerate an 80bit run length. Such a run cannot occur in 64b/66b because transitions are guaranteed at 66 bit intervals.

An earlier scrambler used in Packet over SONET/SDH (RFC 1619, 1994) had a short polynomial with only 7 bits of internal state which allowed a malicious attacker to create a Denial-of-service attack by transmitting patterns in all 27-1 states, one of which was guaranteed to desynchronize the clock recovery circuits. This vulnerability was kept secret until the scrambler length was increased to 43 bits (RFC 2615, 1999) making it impossible for a malicious attacker to jam the system with a short sequence.

64b/66b avoided this vulnerability by using a scrambling polynomial with enough random internal state (58 bits) that it was provably impossible for a dedicated attacker to force a 64 bit run-length pattern any more effectively than sending random data.

Similarly, the DC balance of 64b/66b is not absolutely bounded. However, it can be shown that the scrambler output closely approximates a sequence of random binary bits. Passing such a sequence through an AC-coupled circuit produces a "baseline wander" that follows a gaussian distribution, and the impact on the system error rate can be statistically quantified. In practice, a modest coupling capacitor value of 0.001uF in a 100 ohm system is sufficient to guarantee that a DC drift of more than 2.5% will occur less often than once per 1022 bits (about 31,700 years at 10Gbit/s).

The main contribution of 64b/66b is the observation that the deterministic runlength and transition density of 8b/10b are not always worth a 25% code overhead, and that solid robust systems could be designed using statistically bounded methods. At some point, the real risk of a nuclear war, meteoric impact, or power supply failure dominate the reliability of both 8b/10b and 64b/66b systems.

If the DC balance of 64b/66b is not sufficient for some application (such as a requirement for using small coupling capacitors implemented on chip), the Interlaken protocol improves the DC balance further by trading off more coding bits. By using the 64b/67b encoding. 64b/67b extends 64b/66b with explicit DC balancing.