4000 Series - Design Considerations

Design Considerations

The original 4000 series was available in either unbuffered or buffered inputs and outputs. The buffered outputs can source or sink more current than the unbuffered outputs, eliminating the need for discrete switching transistors in some designs. The buffered versions also have faster output switching times, as the signal rise time of the buffered output stage is faster than that of an unbuffered device. However the overall propagation delay through the buffered versions is higher due to the additional circuitry. The buffered devices are more susceptible to output oscillation with slow-changing inputs. Designers must evaluate the choice of buffered or unbuffered parts according to the nature of the circuit in which the devices are being used. The additional input and output gates on the buffered parts also make them marginally less susceptible to damage by electrostatic discharge (ESD).

Although the original designation for unbuffered and buffered parts was the addition of an 'A' or 'B' suffix to the part code (e.g.: 4000A = unbuffered, 4000B = buffered), some manufacturers (e.g.: Texas Instruments) later changed to using UB (unbuffered) and B (buffered) suffixes (e.g.: 4000UB and 4000B).

The diagrams below show the construction differences between a simple buffered and unbuffered CMOS NOR logic gate. Note that the logic gate at the core of the buffered part is actually a NAND gate, but the overall function of the complete circuit is a NOR gate due to the logic inversions performed by the buffers. (A negated NAND with negated inputs becomes a NOR as defined by De Morgan's laws in Boolean Algebra.) The clamping diodes on the inputs are to offer some protection against ESD.

The 4000 series permits the use of "cookbook" design, where standard circuit elements can be created, shared, and connected to other circuits with few, if any, connection difficulties. This greatly speeds the design of new hardware by reusing standard approaches to circuit design. In contrast, TTL circuits, while similarly modular, often require much more careful interfacing, since the limited fanout (and fan-in) require that the loading of each output be carefully considered. (Some later TTL families, like 74LS reduce this problem with fanouts of 20.) It is also much easier to prototype LSI designs using the 4000 series and get repeatable and transferable results when moving to the more integrated design.

Some care needs to be taken with the design of circuits using CMOS chips. Many parts offer multiple logic gates in a single package and it is common to not need all of them. An engineer who forgets to 'tie off' (connect the unused gate inputs to VSS or VDD) may find the chip draws excessive current. The problem is caused by biasing in each gate. With the inputs disconnected, the gates may be biased into a mode where the outputs are partially conducting; this leaves the output buffer drawing a great deal of current since it is not fully on or off, creating a low resistance current path between the power supply rails.