32 Nanometer - Technology Demos

Technology Demos

Prototypes using 32 nm technology first emerged in the mid-2000s. In 2004, IBM demonstrated a 0.143 μm2 SRAM cell with a poly gate pitch of 135 nm, produced using electron-beam lithography and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale. In October 2006, the Interuniversity Microelectronics Centre (IMEC) demonstrated a 32 nm flash patterning capability based on double patterning and immersion lithography. The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node. TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm2 six-transistor SRAM cell in 2005.

Intel Corporation revealed its first 32 nm test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182 μm2, used a second-generation high-k gate dielectric and metal gate, and contained almost two billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers. The critical pitch was 112.5 nm.

In January 2011, Samsung completed development of what it claimed was the industry's first DDR4 DRAM module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30 nm-class process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 DRAM to consume just half the current of DDR3 when reading and writing data.