The 22 nanometer (22 nm) is the next CMOS process step following the 32 nm step on the International Technology Roadmap for Semiconductors (ITRS). The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first introduced by semiconductor companies in 2008 for use in memory products, while first consumer-level CPU deliveries started in April 2012.
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.
On the ITRS roadmap, the successor to 22 nm technology will be 14 nm technology.
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