The 16550 FIFO
One drawback of the earlier 8250 UARTs and 16450 UARTs was that interrupts were generated for each byte received. This generated high rates of interrupts as transfer speeds increased. More critically, with only a 1-byte buffer there is a genuine risk that a received byte will be overwritten if interrupt service delays occur. To overcome these shortcomings, the 16550 series UARTs incorporated a 16-byte FIFO with a programmable interrupt trigger of 1, 4, 8, or 14 bytes.
Unfortunately, the original 16550 had a bug that prevented this FIFO from being used. National Semiconductor later released the 16550A which corrected this issue. Not all manufacturers adopted this nomenclature, however, continuing to refer to the fixed chip as a 16550.
The 16550 also incorporates a transmit FIFO, though this feature is less critical as delays in interrupt service would only result in sub-optimum transmission speeds and not actual data loss.
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