Output Enable Vs. Chip Select
Many memory devices designed to connect to a bus (such as RAM and ROM chips) have both CS (chip select) and OE (output enable) pins, which superficially appear to do the same thing. If CS is not asserted, the outputs are high impedance.
The difference lies in the time needed to output the signal. When chip select is deasserted, the chip does not operate internally, and there will be a significant delay between providing an address and receiving the data. (An advantage of course, is that the chip consumes minimal power in this case.)
When chip select is asserted, the chip internally performs the access, and only the final output drivers are disabled by deasserting output enable. This can be done while the bus is in use for other purposes, and when output enable is finally asserted, the data will appear with minimal delay. A ROM or static RAM chip with an output enable line will typically list two access times: one from chip select asserted and address valid, and a second, shorter time beginning when output enable is asserted.
Read more about this topic: Three-state Logic
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